1. Field of the Invention
The present invention is related to a pipeline processor, and more particularly to one having a hardware loop function with a terminating instruction which can terminate a loop processing by returning the content of a stack to a program counter according to the status indicated by a operation flag as well as a value of a loop counter during the loop processing.
2. Description of the Related Art
Processors of the prior art are constructed so that instructions are executed one by one, that is, only after completion of execution of one instruction, execution of the next instruction is started. In order to improve the efficiency of instruction execution of the processor of the prior art, the pipeline method was developed as one of the solutions and is now generally utilized.
In the pipeline method, the execution of one instruction is divided into several stages such as, for example, an "instruction fetch" stage, an "instruction decoding" stage and an "executing operation etc." stage. At the moment the execution of the instruction starts in the "executing operation etc." stage, decoding the next instruction starts in the "decoding" stage, and fetching the second next instruction starts in the "instruction fetch" stage; and thus the apparent execution efficiency improves, almost three times in this example.
The instructions comprising a program are usually stored in the instruction memory. When the program has a repetitive structure wherein a single instruction or several of them are respectively used, a loop program is made by using the conditional branch instructions in order to decrease the storage requirements in the instruction memory.
When an instruction sequence is accompanied by a branch, the operation result relating to the instruction having been already executed in the pipeline are invalidated and the instruction of a branch destination is fetched into the pipeline. In this case, the instruction execution efficiency is lowered. To cope with this problem, in case of simple repetitive processing of several instructions, the number of repetitive times of a loop instruction, a loop start address and a loop end address are held in the registers or the like by the loop start instruction, and the loop processing is controlled by hardware in parallel with the execution of the operations; in this way, the invalidation of the pipeline at the loop end including the branch is prevented. This technique is disclosed, for example, in "DSP56000 Digital Signal Processor User's Manual", pp. 7-20 through 7-21 published by Motorola.
Further, when the instruction sequence must escape the loop depending on the execution results of the operations in the loop as well as the simple repetitive processing, a loop escape instruction is provided. This technique is disclosed in the above papers, pp. A-71 and A-72.
However, abovementioned loop escape instruction is only used together with so called a conditional jump instruction, and the operations and data transfers cannot be done simultaneously with the loop escaping processing, therefore the data processing efficiency in the loop is lowered.